1. Fields of the Invention
The present invention relates to an in situ pulse-based delay variation monitor that predicts timing errors caused by process and environmental variations, especially to an in situ pulse-based delay variation monitor that predicts timing errors caused by a process and environmental variation in which a transition detector and pulse width are used to replace traditional error prediction flip flops. Traditionally, the in situ error prediction circuit senses the timing error by comparing the data between the main flip flop and the canary flip flop among a user defined prediction window. However, in the present invention, a pulse detector technique is adopted to predict the timing error instead of the canary flip flop for power reductions and area savings. Moreover, the function of error detection is also added. Thus users still know whether the correct data is captured or not even the clock signal is over the checking time. And the circuit is used as a performance monitor for components that support the adaptive voltage scaling. The components can be processors, microprocessors, central processing unit (CPU), digital signal processor (DSP), etc.
2. Descriptions of Related Art
With scaling of advanced process technology, variations in process, voltage and temperature (PVT) that could cause timing errors during operation of microprocessors are increasingly significant. Traditionally, IC designers consider the worst case conditions and use a large safety margin to increase the tolerance of process, voltage and temperature variations. The system designed under such a pessimistic assumption may consume unnecessary power consumption and occupy extra area simultaneously. Therefore, adaptive designs, such as adaptive voltage scaling or adaptive frequency scaling, becomes an indispensable technique for eliminating large safety margins. According to the results of the PVT variation detectors, the unacceptable energy and performance loss can be mitigated by adaptively controlling the supply voltage or operating frequency.
Especially an IC design with ultra-low supply voltages, process variations leads to quite large variations in circuit operation time. For normal operation considering all the variations, the circuit runs based on the worst-case voltage to ensure all the functions are executed correctly. However, this causes a lower energy efficiency of the circuit. Thus the solution is to adjust the operating voltage dynamically by a mechanism that can detect process variations and avoid operating at the worst case under all conditions.
Generally in situ detection mechanism is divided into two groups according to retrieving form of wrong timing data. One is error detection mechanism. After the data being retrieved, whether there are errors in the retrieved data caused by timing errors can be checked. For example, referring to U.S. Pat. No. 8,185,812, a single event upset error detection within an integrated circuit is revealed. It uses a technique referred to “Razor” that allows voltage safety margins providing for uncertainties in silicon and ambient conditions to be eliminated or reduced. In general, the Razor technique involves adjustment of the operating parameters of an integrated circuit, such as the clock frequency, the operating voltage, the body bias voltage, temperature and the like so as to maintain a finite non-zero error rate in a manner that increases overall performance. Errors are detected in the processing stages by comparing a non-delayed data value with a delayed data value. The single event upset error detection within an integrated circuit includes a plurality of steps. Store a sampled input signal within a sequential storage element. Then detect a transition of the single stored signal value stored by the sequential storage element occurring at a time outside a valid transition period as indicating an error by combinatorial logic. However, the shortcoming of the above method is in that errors can only be detected after the errors occurred and a period of time for recovery is required after detection of the errors. Thus once the errors occurred, the power overhead is significant.
The other in situ detection mechanism is error prediction mechanism, which focuses on whether the timing errors possibly occur can be predicted in advance before errors actually occur. Generally, the error prediction mechanism including a main flip-flop and a canary is applied only to compare input signals within a checking period preset by designers. Moreover, the error prediction circuit still has prediction errors in its existed concept of design. If the timing signal is over the checking period preset by designers, whether the correct data is captured or not is unable to be learned.